The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 1978
Filed:
Mar. 04, 1977
Applicant:
Inventors:
Hiroo Sakaba, Kodaira, JP;
Kenzo Masuda, Tokorozawa, JP;
Assignee:
Hitachi, Ltd., , JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; G11C / ;
U.S. Cl.
CPC ...
307205 ; 3072 / ; 307207 ; 307213 ; 307215 ; 357 23 ; 365104 ;
Abstract
A ratioless type MIS logic circuit comprises a logic block including at least one depletion mode FET inherently having a gate-to-source parasitic capacitance and a gate-to-drain parasitic capacitance, an output capacitance, a circuit for precharging the output capacitance and depletion mode clamping FETs connected one with each of the two ends of the logic block, the clamping FETs having their gates connected with a reference potential and the threshold voltage value of the FET in the logic block being larger than those of the clamping FETs.