Frequency synthesizer with phase locked loop and counter

Abstract

A frequency synthesizer including a phase-locked loop (PLL) is provided which does not use any variable frequency divider. The output of a reference frequency oscillator is applied to a phase comparator in the PLL through a monostable multivibrator. The oscillating frequency of a voltage controlled oscillator (VCO) in the PLL can be selected by controlling a bias DC voltage applied to a control element in the VCO. The output waves from said VCO are counted at a counter during a period of the reference frequency from the reference frequency oscillator of the PLL. The count operation is repeated at a predetermined time interval. After completion of each count operation, the number in the counter corresponding to the least digit column of the decimal number is discriminated to determine whether it is within a predetermined range or not. The range is determined correspondingly to a locking range of the PLL. When it is within the range, the PLL is placed into an operating condition to stabilize the oscillating frequency of the VCO at a desired frequency. Also, the counted number is indicated by an indicator. The number in the counter corresponding to the least digit column of the decimal number may be converted into an analogue signal to automatically control the oscillating frequency of the VCO.