Timing pulse generator

Abstract

A timing pulse generator for testing electronic components such as semiconductor memories, which tests require time accuracy and repeatability. A number of registers are provided for registering digital words which correspond to timing pulses to be generated. Each word includes information in a first portion as to the coarse start time of a particular pulse and information in a second portion as to the fine start time of the pulse. A counter circuit is provided with means for starting and stepping the counter in pedetermined increments through a plurality of states. A digital comparator compares the state of the counter with the coarse start time portion of the word stored in the register and generates an output pulse when the two coincide. A digitally controlled variable delay circuit is provided corresponding to each register. An output from the register corresponding to the fine start time portion of the word sets the amount of delay introduced by the delay circuit. The output pulse from the digital comparator is applied to the delay circuit such that the pulse is delayed by an amount determined by the fine start time information in the word stored in the register. The counter start control means enables automatic switching between triggered and gated modes for single cycle or continuous cycle operation of the counter without false triggering of the counter.