Sense line balance circuit for static random access memory

Abstract

A random access memory includes a column of static MOS storage cells. Two sense-write write conductors are coupled to each cell in the column. The first sense-write conductor of each column of storage cells is coupled by means of a first coupling MOSFET to a first bit-sense conductor. The second sense-write conductor of each column of storage cells is coupled, by a second MOSFET to a second bit-sense conductor. Each sense-write conductor is coupled to the other by a first MOSFET having its gate electrode coupled to a circuit for generating a pulse in response to an address input transition. A second balancing MOSFET is coupled between the two bit sense conductors and has its gate also coupled to said circuit. Since at the end of any read or write operation, the two bit sense conductors and the two sense-write conductors of the selected column will be at opposite voltage levels, the output pulse equalizes the voltages of the two sense write conductors and of the two bit sense conductors at a level approximately midway between the voltages of a power supply conductor and ground, so that during the next read cycle the cell need only discharge one of the sense-write conductors and the corresponding bit sense conductor coupled thereto from the midway voltage level to ground, thereby considerably reducing the access time of the memory.