Electronically alterable non-latching josephson and, or, nand, nor logic

Abstract

An electronically alterable logic circuit is disclosed which provides different logical outputs which are a function of control signals applied to the circuit. More specifically, a non-latching Josephson junction circuit is provided which is capable of providing true and complementary outputs at a pair of output terminals when at least one pair of a plurality of pairs of fixed biases are applied to a plurality of serially arranged Josephson junction devices. The Josephson devices are arranged so that a true output can be obtained from an output circuit which shunts a pair of Josephson devices while the complement of the true output can be obtained at an output circuit which shunts an appropriately biased Josephson junction which is disposed in series with the above mentioned pair of Josephson junctions. The complementary output is achieved by utilizing a portion of the output circuit which shunts the pair of Josephson junctions as a control line for the single Josephson junction in series with the pair of Josephson junctions. The current through the control line portion, when present, opposes a bias current setting up a situation such that when current flows in the output representative of a true output, no current flows in the output representative of a complementary signal and vice versa. In addition to achieving true and complementary outputs which can be characterized as AND, NAND, OR and NOR outputs, it has been recognized that these same outputs can be attained at the complementary output by simply applying binary combinations of biases to the two bias lines associated with the logic circuit.