The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 1978

Filed:

Sep. 03, 1976
Applicant:
Inventor:

Ryuji Toida, Nagoya, JA;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G08C / ; H03K / ;
U.S. Cl.
CPC ...
3403 / ;
Abstract

A reading system for a hybrid A-D converter having, in combination, code disk A-D converters for converting an analog quantity such as a rotation angle or the like into a digital quantity and a neighborhood absolute value detector such as an inductosyn, a resolver or the like for providing the absolute value of a rotation within a small range thereof to, thereby extend the neighborhood absolute value region. Each of the code disk A-D converters supplies an output signal l and a carry signal Cr(1) which is generated depending on whether an output signal from a lower order code disk A-D converter is included in a predetermined upper group to a corresponding one of the logical circuits which are provided so as to correspond in number to the code-disk A-D converters. The logical circuit performing the logical operation L = l .multidot. (Cr.multidot.l-1+Cr.multidot.l+1) provides a signal representative of one digit whereby the outputs from the A-D converters are prevented from errors upon carrying. The neighborhood absolute value detector supplies a carry signal Cr(2) depending on whether the neighborhood absolute value is included in the predetermined upper group. The carry signal Cr(2) and the inverted signal Cr(2) of the carry signal Cr(2) are adapted to be supplied to the logical circuit in time-sharing relation to the carry signal Cr(1) and the inverted signal Cr(1) of the carry signal Cr(1).


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