Chronometric system with several synchronized time-base units

Abstract

Three identical time-base units include respective binary counting circuits which are stepped in parallel by a series of clock pulses to generate trains of timing pulses and, after a certain number of clock cycles following resetting by a zeroizing pulse, emit synchronizing pulses which are jointly fed to three decision networks respectively associated with these counting circuits. The decision networks determine by majority logic whether synchronizing signals from at least two of the three counting circuits coincide and upon such coincidence cause the resetting of the respective counting circuits to zero. A monitoring circuit, also operating by majority logic, is connected to the three decision networks to indicate a malfunction of any of the three time-base units without halting the generation of the timing pulses by the defective unit if the latter is merely out of step. The clock pulses are obtained by each counting circuit from a square-wave oscillator through a switchover circuit which, upon detecting failure of that oscillator, replaces it within a fraction of a clock cycle by a standby oscillator whose own operating condition is also continuously checked. Each counting circuit includes a primary counter and a secondary counter stepped in parallel but with a relative offset to allow for differences in transit time of the synchronizing signals sent to the three decision networks.