The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 1978

Filed:

Sep. 29, 1976
Applicant:
Inventors:

James Grant Dunn, Upper Montclair, NJ (US);

Philip Duncan Carmichael, Closter, NJ (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02B / ;
U.S. Cl.
CPC ...
325 30 ; 325163 ; 325320 ; 179 / ; 178 67 ;
Abstract

In the transmitter portion a multiplexer multiplexes first digital data and first teletype signals to provide first digital data signals. The first digital data signals are converted into second digital data signals having a different form than the first digital data signals by a Viterbi coder. A PSK modulator responsive to the second digital data signals provides a first PSK signal for transmission. In the receiver portion a PSK demodulator receives a second PSK signal containing third digital data signals having multiplexed second digital data and second teletype signals with the third digital data signals being extracted from the second PSK signal. A Viterbi decoder converts the third digital data signals into fourth digital data signlas having a different digital form than the third digital data signals. A PSK demultiplexer is responsive to the fourth digital data signals to separate the second digital data and the second teletype signals for utilization. The arrangement to extract the third digital data signals from the second PSK signals includes the PSK demodulator and a Costas' type phase locked loop including a number controlled oscillator, a digital phase shifter, an accumulator arrangement including three accumulators accumulating different data and errors, a clock recovery circuit and a loop filter controlling the number controlled oscillator.


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