Circuit arrangement for monitoring the function of a dynamic decoder

Abstract

A circuit arrangement for monitoring the function of a dynamic decoder circuit which comprises at least parallel-connected decoder transistors, a pre-charging transistor, and an end stage which samples the output signal of the decoder transistors, is disclosed in which for simulating the decoder circuit, two discharge transistors are connected in parallel and have control inputs which are supplied with address signals in inverted form and in non-inverted form and whose node, which is formed by the one connection point, is precharged in that it is connected to a further transistor. In order to simulate the capacitance existing at the corresponding connection point of the parallel-connected decoder transistors of a decoder circuit, a varactor is connected to the node and the node is also connected to the further circuit elements provided in the decoder circuit between the decoder transistors and the end stage. For simulating the capacity load formed by the end stage of the decoder circuit, a further varactor is provided which is subsequently connected to the further circuit elements.