Uncertain interval timer using a variable length shift register

Abstract

A composite shift register timer for controlling a sequence of events occurring over a demand-response interface. The composite shift register comprises a primary shift register and a secondary shift register. The primary shift register is divided into successive portions which are selectively coupled together in successive pairs upon timely receipt of respective response signals. A first binary '1' is inserted into the first portion at the start of a predetermined sequence of events. The first '1' is clocked through to the end of the first portion where it initiates a demand and is stored pending the receipt of a corresponding response. A second binary '1' is clocked through the secondary shift register beginning with the initiation of each demand. The clocking of the second '1' continues until the receipt of a timely response to the initiated demand whereupon the secondary shift register is reset. The timely response also is applied to the coupling means between the first and second portions of the primary shift register to permit the stored first '1' to propagate into and be clocked through the second portion. If no timely response is received, the second '1' propagates to the end of the secondary shift register to produce an 'error' signal. The error signal deactivates each coupling means between the portions of the first shift register to prevent the first binary '1' from propagating any farther, thus terminating the sequence of events.