The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 10, 1978
Filed:
Dec. 13, 1976
George Erdi, Palo Alto, CA (US);
Precision Monolithics, Inc., Santa Clara, CA (US);
Abstract
An integrated circuit including an FET and an analog for cancelling input current that would otherwise be required to supply the FET gate leakage current. The analog establishes a leakage current the magnitude of which is a substantially fixed proportion of the FET leakage current over a given operating range, and employs proportional current mirror means referenced to the analog leakage current to supply the FET leakage current and thereby substantially cancel the input bias current. In a preferred embodiment the analog comprises a lateral PNP multi-collector transistor with one collector connected to its base to establish a reference current, another collector providing the cancellation current, and its base voltage tracking the FET gate voltage so that the two leakage currents remain substantially equal. An analog FET may also be employed to cancel gate-to-drain and gate-to-source leakages. A description of the invention as applied to an operational amplifier is given.