The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 1978

Filed:

Oct. 04, 1976
Applicant:
Inventor:

Robert K Likuski, Castro Valley, CA (US);

Assignee:

Micro-Bit Corporation, Lexington, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365237 ; 365174 ; 365118 ; 11C / ;
Abstract

A method and apparatus for deep depletion read-out of data stored in a metal-insulator-semiconductor-metal capacitor memory element wherein a predetermined read-out potential is established across the memory capacitor while discrete storage sites within the capacitor are interrogated by a scanning electron beam probe and the magnitude of the resultant memory capacitor discharge current obtained from probing a particular site with the electron beam is indicative of the character of data stored at the site. The improvement comprises applying a voltage step across the capacitor memory element just prior to read-out with the electron beam, the voltage step corresponding in polarity to the polarity of the majority carriers in the semiconductor. In one embodiment of the invention the capacitor memory element employing two electrical contacts is comprised by a gate metal layer-oxide insulating layer-P-type semiconductor-metal backside layer and the voltage step is a positive going voltage step occurring at the trailing edge of a negative voltage pulse applied to the gate metal layer relative to the backside metal layer from a source of variable potential. The negative voltage pulse is either applied just prior to the commencement of each line of scan of the electron beam probe or immediately prior to the commencement of a succession of scans of the electron beam probe. The pulse is followed by a steady state value of read-out potential. In a preferred form of the invention, a capacitor memory element employing two electrical contacts and including an N-type semiconductor layer overlying a substrate P-type semiconductor layer and covered by an oxide insulator layer is employed with similar pre-read biasing treatment.


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