Ultimate density non-volatile cross-point semiconductor memory array

Abstract

An extremely high density memory array in which every intersection between two insulated orthogonal sets of drive lines define a nonvolatile memory device is described. Each device utilizes the area directly under the intersection of sets of lines to selectively store charges therein under control of suitable writing pulses. Reading is accomplished utilizing capacitive coupling through the device. The array comprises insulated metallic word lines orthogonal to doped bit lines defined within the surface of a semiconductor body. The insulation between the word lines and the bit lines has a dual charge state and is capable of storing charges. A unique structure is utilized whereby a highly doped layer is formed at the surface of the semiconductor body and of the same conductivity type as the body. The bit lines are composed of two distinct layers of an opposite conductivity type to that of said body wherein the layer closest to the surface is less highly doped. The selective biasing of word and bit lines causes charges to be injected into the insulation immediately between the two lines which injected charges alter the capacitance characteristics of the device and thus the signal coupling characteristic between the word and bit lines. During the write operation, an avalanche breakdown at the junction is caused to occur by heavily biasing the junction, and charge carriers are injected into the overlying insulator. The charge carriers so injected remain localized in the insulator immediately between the two lines with negligible fringing into the region outside this intersection and thus do not disturb the information on adjacent bit lines which allows extremely close placement of such adjacent lines. To erase, a voltage is supplied to cause the injected carriers to be driven out of the insulation back into the substrate. As stated previously, the reading operation utilizes the change in the coupling capacitance with a charge stored in the device and comprises introducing a signal on one line well below the breakdown voltage of the device so that the stored charge is in no way affected by any number of reading operations and detecting said signal on the other line, if coupled through.