Solid state threshold detector with hysteresis

Abstract

An apparatus for providing an output digital signal when the magnitude of a monitored parameter is within a critical range. An oscillator repeatedly charges each of first and second capacitors to a predetermined voltage level. A monitoring resistor is parallel coupled with the first capacitor and has a resistance progressively changing with the magnitude of the parameter to define a rate of discharge of the first capacitor, between repeated chargings, determined by the parameter. A reference resistor is parallel coupled with the second capacitor and has a resistance equal to the resistance of the monitoring resistor when the magnitude of the monitored parameter is at the threshold of the critical range and defines a first reference rate of discharge of the second capacitor between repeated chargings. The voltages across the first and second capacitors are monitored by respective threshold detectors, each of which provides an output when the voltage across the respective capacitor exceeds a specified level. The outputs of the threshold detectors are coupled to a logic circuit which compares the duration of the outputs of the threshold detectors and generates an output when the duration of the output of the level detector monitoring the first capacitor varies from the time duration of the output of the level detector monitoring the second capacitor in a sense representing a critical magnitude of the condition. A circuit is responsive to the output of the logic circuit to couple a third resistor in parallel with the reference resistor to define a second reference rate of discharge of the second capacitor between repeated chargings so as to provide a hysteresis in the output signal from the logic circuit in response to variations of the monitored parameter.