The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 1977
Filed:
May. 12, 1976
Lewis K Russell, San Jose, CA (US);
Signetics Corporation, Sunnyvale, CA (US);
Abstract
Unidirectional and bidirectional bipolar logic transmission gates have an input, an output, a gate control, supply and common terminals. The unilateral transmission gate circuit includes first and second switching transistors and associated first and second source tranisistors. The transistors each have collector, base and emitter electrodes, said first source transistor emitter being connected to said supply terminal. The collector of the first switching transistor is connected to the base of the second switching transistor and defines a gate logic node. The base of the first switching transistor is connected to the first input terminal and the collector of the second switching transistor is connected to the output terminal with both switching transistor emitters being connected to the common terminal. Gate switching means is connected between said gate logic node and said gate control input, said means being responsive to first and second logic levels at said gate control input for driving said gate logic node to first and second states causing the transmission gate to assume open and closed states from input to output. A bidirectional bipolar logic transmission gate includes an additional gate logic node and gate switching means simultaneously drives said gate logic node and additional gate logic node to first and second states causing the transmission gate to assume bilateral open and closed states between said first and second input and output terminals.