The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 13, 1977
Filed:
Jul. 06, 1976
Ruediger Mueller, Munich, DT;
Siemens Aktiengesellschaft, Berlin & Munich, DT;
Abstract
A logic circuit has the individual elements arranged in a semiconductor layer. The elements are in the form of field effect transistors having a multiple gate and bipolar transistors having a multiple emitter. The multiple gates of the field effect transistor represent the inputs of the fundamental logic circuit, and at least one emitter of the multiple emitters of the bipolar transistor represents the output of the fundamental logic circuit. The elements are arranged in the semiconductor layer in such a manner that a first supply voltage potential can be connected to the semiconductor layer. One configuration of the multiple gates of the field effect transistor identifies the circuit as a NAND circuit, while another configuration of the gates identifies the circuit as a NOR circuit. An additional element, a bipolar transistor, may be formed in the semiconductor layer and be connected to an emitter of the multiple emitter transistor to provide a power output stage in a Darlington configuration.