Circuit arrangement for diversity data transmission

Abstract

A circuit arrangement is described for carrying out a diversity selection from a number of data channels. The diversity channels are connected to a majority logic decision stage. The diversity channels and the output from the majority logic stage are connected to a channel switch as data channels. By means of a quality evaluation stage, one of the diversity channels is switched through to the data bank under the control of signals produced responsive to an indication that a minority of the diversity channels is better than each of the remaining diversity channels by a given quality difference. The majority decision channel is switched through with one of the control signals when the majority of the diversity channels are poorer than the remaining diversity channels during the given test period by another given quality difference.