The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 1977

Filed:

Jun. 30, 1976
Applicant:
Inventors:

Sumit Das Gupta, Syracuse, NY (US);

Edward Baxter Eichelberger, Purdy Station, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364700 ; 328 62 ; 364200 ;
Abstract

Disclosed is an improved clock generation network. The improved clock generation network is particularly adapted to, and has particular utility when employed in a Level Sensitive Logic System generally of the type disclosed in U.S. Pat. No. 3,783,254, of common assignee. The disclosed clock generation network also has particular utility in a Level Sensitive Embedded Array Logic System of the type disclosed in U.S. patent application Ser. No. 701,052, filed June 30, 1976, by Messrs. E. B. Eichelberger, E. I. Muehldorf, R. G. Walther and T. W. Williams and of common assignee.


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Das Gupta, Sumit. (1977). Clock generation network for level sensitive logic system (U.S. Patent No. 4063078). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4063078

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