Charge coupled device random access memory

Abstract

Semiconductor memory cells include gate conductor-insulator-semiconductor regions having storage and transfer portions in which the threshold voltage and surface potential-gate conductor voltage characteristics differ as between the storage and transfer portions. This may be achieved by employing relatively thick and relatively thin insulator areas at the storage and transfer portions, or vice versa, with a surface charge accumulation layer at the semiconductor region insulator interface. In a different form of cell structure, the insulator is a uniform thickness layer overlying the storage and transfer portions one of which includes a doped semiconductor region of the same conductivity type as, but higher dopant concentration than, the remainder of the semiconductor region. The difference in threshold voltage and surface potential characteristics is such that in response to first and second defined gate voltage levels, the potential well profile at the storage and transfer portions is changed in a manner permitting write in and read out of logic signal level related charge packets into and from the storage portion. Semiconductor memories include a matrix array of such cell structures, the gate conductor of a line of cells in the matrix forming part of a store/word conductor common to that line and a sense portion of each cell may form part of a common sense line for a line of cells extending perpendicularly to the store/word conductors. The memory cells may be fabricated by a process utilizing photolithographic alignment offset and self-aligning techniques in conjunction with diffusion and ion implantation techniques.