Dual testing system for supervising duplicated telecommunication

Abstract

Two processors UP1 and UP2, designed to test the operation of a pair of switching networks IN1 and IN2 in a telecommunication system through respective sets of peripheral interface units P11 etc. and P21 etc., are interconnected for parallel operation and are each linked with both sets of peripheral units via branched output and input multiples carrying outgoing and incoming messages. Each set of peripheral units is served by a respective bus bar BUS1, BUS2 connectable at one end, via an outgoing multiplexer MX12, MX22, to one of the branches of either output multiple 2, 3 and at the other end, via an incoming multiplexer MX11, MX21, to one of the branches of either input multiple 12, 13. The outgoing messages are also delivered, in parallel, to a pair of decision networks LS1, LS2 controlling the associated multiplexers MX12, MX22 in response to switching criteria obtained from a pair of intercommunicating synchronization circuits SN1, SN2 which are inserted in the two outgoing multiples upstream of their branching points. The sending of incoming messages from the peripheral units to the processors is preceded by access requests temporarily stored in parallel, under the control of a timing circuit BT, in a pair of buffer registers MT1 and MT2 respectively assigned to processors UP1 and UP2.