Processing link control device for a data processing system processing

Abstract

A data register storing an instruction code field, modification bits, a control bit field, condition branching fields and the next address in corresponding areas thereof is coupled to a control memory via a plurality of AND gates. A branch determination circuit for determining an instruction for selecting in accordance with a machine state, a single micro-instruction of four which are read out from the control memory, is connected to each AND gate for controlling them. The branch determination circuit is connected to the data register's condition branching field areas. A save-restore address register storing the address and branch address bits in corresponding areas thereof is coupled to the data register's next address area, the branch determination circuit, the control memory, from a first branch address bit area thereof to each AND gate for controlling them and is connected to a first bit modification control circuit. The second branch address bit area thereof is coupled to each AND gate for controlling them and is connected to a second bit modification control circuit. A save memory for storing the return address is coupled to the save-restore address register's address area and to the first and second bit modification control circuits. The save memory is coupled to the save-restore address register's address area whereby any of a plurality of return addresses is designated by selection of the modification bit in the branch and link instruction and access is provided simultaneously for four word address positions of the control memory by the next address, four micro-instructions are read out from the control memory by the next address and only one of the four micro-instructions is selected by the condition branching fields via the AND gates and set in the data register.