The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 27, 1977
Filed:
Dec. 16, 1976
Theodore Alan Fulton, Warren Township, Somerset, NJ (US);
Bell Telephone Laboratories, Incorporated, Murray Hill, NJ (US);
Abstract
A superconductive circuit includes a loop circuit having first and second parallel branches connected in parallel with an appropriately terminated fan-out line. Each branch includes a Josephson junction device and the loop circuit includes at least one resistor. A bias current is applied directly to the loop circuit so that each Josephson device is biased below its critical current I.sub.J. A control current is then coupled (directly or inductively) to the loop circuit so that in one branch the bias and control currents add and exceed I.sub.J. The Josephson device in that branch switches from V = 0 to V = 2.DELTA. causing substantially the entire bias current to flow through the other branch and thereby switching the other Josephson device to V = 2.DELTA.. Now substantially all the bias current is diverted to the fan-out line which can be used to control other similar circuits, i.e., to provide either the control or bias current for other circuits. Logic is performed by using multiple control currents coupled to the loop circuit, a resistor in the fan-out line and preferably resistors in each branch. Memory is achieved by forming a totally superconductive closed circuit path including the fan-out line and a portion of the loop circuit.