Level sensitive embedded array logic system

Abstract

A generalized and modular logic system is described for all arithmetic/logical units and their associated control storage and any other arrays. The logic system is partitioned into sections formed of combinational logic networks, storage circuitry, and arrays. The storage circuitry is sequential in operation and employs clocked dc latches. Two or more synchronous, non-overlapping, independent system clock trains are used to control the latches. The array is a rectangular array of storage element, M .times. N where, M is the number of words in the array and N is the number of bits in each word. The array may be read only, or it may be a read/write array. The array may be a programmable logic array (PLA). A single-sided delay dependency is imparted to the system. The feedback connections from the respective latch circuitry are made through combinational logic or an array to other latch circuitry. The clocking of the latches and of the array, if any, are such that the network may be operated in a race free mode. With each latch, there is provided additional circuitry so that each latch acts as one position of a shift register having input/output and shift controls that are independent of the system clocks and the system input/outputs. All of the shift register latches are coupled together into a single shift register. The logic between the latch inputs and the array inputs has the property that a 1 to 1 correspondences can exist between array inputs and the latch inputs. Furthermore, all of the array outputs are uniquely detectable at the latch or primary outputs.