The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 1977
Filed:
Dec. 13, 1974
Alan K Jennings, Anaheim, CA (US);
Pertec Corporation, Los Angeles, CA (US);
Abstract
A medium capacity peripheral processing system provides sophisticated interactive human communication without the extremely large, expensive memory systems that are normally associated with a main frame computer. The system includes a data bus interconnecting a 16 bit parallel processor, a random access memory having up to 64K words of memory storage, up to eight magnetic tape files, up to eight magnetic disk files, a key station multiplexer, and selector channels providing additional communication capabilities. The selector channels permit optional communication with a main frame computer system, a remote data entry system which may be a simple CRT key station or another peripheral processing system, a high speed optical character reader (OCR), a line printer, a computer output microfilm (COM) unit, or other data processing systems or subsystems. The key station multiplexer provides communication of serial address, data and control signals for up to 64 addressable, CRT key station terminals. The CRT key station terminals are dependent upon individual processor generated commands received over a single, bidirectional coaxial cable for each automatic repeat of a data key, each audible tone signal, each key click signal and each modification of the CRT display. Each key station stores a CRT character display of 12 lines of 40 characters each in a buffer which receives only processor initiated information, stores up to three key stroke characters in a key stroke buffer and provides a three bit configuration code indicating one of eight possible keyboard configurations. A single peripheral processing system may thus utilize a single hardware keyboard configuration with any one of up to eight different character configurations being assigned to a given keyboard. The central processor then utilizes the configuration code to select a conversion table stored in memory to convert the key station character code to a standardized character code.