Memory module with selectable byte addressing for digital data

Abstract

A memory arrangement for a digital data processing system that includes a high-speed associative memory unit and a random access back-up unit. The associative memory unit contains a multiple location address memory and a multiple location data memory wherein there is a correspondence between each address location and a data location. Each time a central processor initiates a reading operation, it issues an address to define a data location. If the associative memory unit contains that address at a location in its address memory, it performs a reading memory cycle and transfers data from the corresponding location in the data memory directly to the central processor. If the data is not available in the associative memory unit during a reading operation, or if the central processor is transferring data to the address location during a writing operation, the associative memory unit causes the back-up unit to perform a corresponding memory cycle. If the address memory in the associative memory unit contains a corresponding address, the new data also is transferred to the corresponding location in the data memory. Secondary memory units, such as disk memory units, and input/output units also communicate with the back-up memory unit and the associative memory unit. For example, a disk memory unit may transfer data to locations in the back-up memory unit, and such a device transmits an address to the back-up memory unit during such transfers. If the associative memory unit contains data from a corresponding location, the contents of the addressed location are modified to indicate that the data in the corresponding back-up location has been changed.