Method for composing electrical test patterns for testing ac parameters

Abstract

A method is provided for generating electrical test patterns for testing functional AC parameters of integrated semiconductor circuits from the test patterns used for the more conventional testing of the DC parameters of such circuits. The AC parameters include such factors as rise time, fall time and circuit delays. Starting with a DC pattern known to be sufficient for the DC testing of the circuit to be tested, each increment of the DC pattern which comprises a plurality of parallel bilevel signals is applied to a corresponding plurality of input points in a standard of the circuit, preferably computer simulated. The resulting output is sensed at output points in the circuit standard. Then, one by one, the input signals in the applied increment are changed while the remainder of the signals are maintained at their original levels. When a change in one of the signals produces a corresponding change in the output, this is noted as path for AC testing. Then, there is stored as the first AC increment, a signal pattern wherein all the signals in the increments are maintained at their original levels except the input producing the change in output, which is stored as a pulsed signal. The procedure is repeated for a plurality of signals in the increment and for a plurality of remaining increments in the DC pattern until an AC signal pattern is developed in which all the input points in the circuit standard are pulsed at least once.