The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 1977
Filed:
Jan. 13, 1976
Seiji Kashioka, Kokubunji, JA;
Masayoshi Kameyama, Sagamihara, JA;
Masakazu Ejiri, Tokorozawa, JA;
Takahumi Miyatake, Hachioji, JA;
Hitachi, Ltd., , JA;
Abstract
A feature extraction system comprises first and second memory circuits and a control circuit for controlling a storing period of time when signals are stored in the first memory circuit. The first and the second memory circuits comprise capacitor memory circuits, the time constant of the second memory circuit being larger than that of the first memory circuit. First and second comparators are coupled to the first and the second memory circuit, respectively. Signals supplied to the first memory circuit are compared with the contents thereof by the first comparator, so that the maximum signal thereof within a predetermined period of time controlled by the control circuit is stored in the first memory circuit. After the predetermined period of time, the contents of the first memory circuit are supplied to the second memory circuit and then the first memory circuit operates to store the maximum signal of the signals supplied to the first memory circuit within a next predetermined period of time. Signals from the first memory circuit are compared with the contents thereof by the second comparator in order to extract the maximum signal of the signals from the first memory circuit, which is stored in the second memory circuit, whereby the maximum signal in the signals supplied to the first memory circuit can be accurately extracted.