Mos dynamic random access memory having an improved address decoder

Abstract

In an MOS dynamic random access memory, address input signals are received by individual comparator buffers which generate corresponding individual pairs of complementary address signals in response to respective ones of the input address signals. The pairs of complementary address signals are strobed from the buffers. Each pair of complementary address signals, as strobed from the individual buffers, diverge from a common potential to a pair of stable complementary address signals which are fed to an array of decoder circuits. Each decoder circuit includes an output line which is precharged to a predetermined potential and is selectively discharged in response to the decoded address signals via a plurality of parallel connected decoder transistors. Each decoder transistor includes a gate control electrode for controlling the conduction between first and second other terminals of the respective transistors. The first terminals are connected to the decoder output line. The pairs of complementary address signals are applied between the gate and second terminals of respective ones of the decoder transistors such that as the complementary address signals diverge sufficiently in amplitude to exceed the turn-on threshold of the individual decoder transistors, those transistors will be rendered conductive for discharging the output line of the respective decoded circuit. Thus, the timing for strobing of the decoder circuit is automatically obtained by the pairs of complementary output signals of the respective address buffers and these address signals need not be held at any predetermined voltage during precharging of the respective decoder output line.