Data processing internal communications system having plural time-shared

Abstract

A memory subsystem is connected to an addressable port on one bus and a non-memory subsystem is connected to an addressable port on another bus. Access to the memory is achieved by the non-memory subsystem by generating a message having a destination code indicating an address on its own bus. An inter-bus communication adapter is connected between the buses and intercepts the requesting message. The message is transmitted by the adapter while the destination code is altered to indicate the address of the memory subsystem on the other bus. The receiving memory subsystem responds by generating a response message and placing the source address into the destination address position of the message. The message is transmitted on the bus to which the memory is connected and is intercepted by a second inter-bus communications adapter. The second adapter transmits the response message to the first bus for application to the requesting subsystem.