Microprogrammable data processor with a microprogram buffer memory

Abstract

A control unit for a processor, which can be controlled by microprograms, in a data processing system utilizes a microprogram memory into which recordings can be made (writable control memory), which exibits an access time which is greater than the machine cycle. The apparatus has an address register which is connected to the selector inputs of the memory and a microcommand register which is connected to the information outputs of the microprogram memory. A decoder unit is connected to the register and serve to derive control signals for a processing unit of the processor from a microcommand in the microcommand register. A switching network is arranged between the microcommand register and the address register and serves to form the address of the following microcommand. The apparatus is particularly characterized in that the information outputs of the microprogram memory are connected to the inputs of the microcommand register, both directly and indirectly via a buffer memory which exhibits an access time which is considerably less than that of the microprogram memory. The memory cells which each store a microcommand can be selected by the low-value bit positions of an entry in the address register and the buffer memory is assigned a marker network in such a manner that with the aid of the low-value bit positions of the entry in the address register, an entry in a storage position of the buffer memory can be marked as valid.