Key register controlled accessing system

Abstract

A plurality of key register sections in a processor respectively associated with different machine-sensed types of accesses to a main storage of a computer system. A processor address key register (AKR) includes the following sections: (1) a section associated with an instruction-fetch type access, (2) a section associated with a source-operand fetch type access, and (3) a section associated with a sink-operand store/fetch type access. Other key register sections may be associated with respective sub-channel store/fetch type accesses. Circuits are provided which sense the different access types to select and outgate a key contained in the corresponding key register section. The values of the keys are associated with different addressabilities (i.e. address spaces). Each different key value is associated with a different stack of translation registers for containing the block addresses in real storage currently assigned to the respective addressabilities. Each key outgated from a respective register section selects an address space by selecting the associated stack of addressing registers to relocatably translate a logical address to a physical storage location within the address space selected by the outgated key.