Error correction circuit utilizing multiple parity bits

Abstract

An arrangement for correcting errors in words read from a memory due to a bit in a word location of the memory being stuck in one of the two binary states, 0 or 1. The arrangement is used in cooperation with parity error detection arrangements which utilize more than one parity bit per word. Upon detection of a single parity failure in a word read from a selected word location in memory the complement of the data word which is indicated to contain a parity failure is placed in the selected word location; the memory is read at the selected word location and the data so obtained is placed back into the selected word location of the memory. After this step the data in the selected word location of memory comprises the complement of the correct data word and the parity bits are all the complement of the correct parity for that data word. The correct data word for use by the processor is thus generated by complementing this later received data. On subsequent reading of the memory at a previously failed location the corrected word in the location is recognized as such by a failure of all of the parity bits. A word in which all of the parity bits fail is automatically complemented and the result is utilized in the data processor.