Priority interrupt logic circuits

Abstract

Priority interrupt apparatus includes a level priority network, a plurality of priority networks, and selector circuits, each corresponding in number to the number of channel sources operative to generate interrupt requests. Each priority network receives requests signals corresponding to different types of possible event signals requiring attention and produces a type code designating the highest priority event from the channel associated therewith. The priority is established in accordance with a preassigned event priority approximating the priorities assignable by program. Each of the selector circuits is connected to receive as a control input the type code signals generated by the priority network associated therewith. Additionally, each selector circuit receives a different set of interrupt level number signals representative of priorities assigned by program to the number of possible event signals. In response to the request signals, the selector circuit of each channel source applies as an input to the level priority network the programmed designated set of interrupt level number signals specified by the type code signals. The level priority network includes a number of compare circuits and output gating circuits. Each compare circuit provides signal indications as to which one of a pair channels has the higher priority event as defined by the selected interrupt level signals. Signals indicating the results from each compare circuits are then applied to the output gating circuits which generate a code for selecting the type code and interrupt level signals of the channel source receiving the highest priority event.