The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 1977

Filed:

Sep. 12, 1975
Applicant:
Inventors:

Jean Pierre Rioult, Epron, FR;

Raymond Fabien, Douvres la Delivrande, FR;

Assignee:

U.S. Philips Corporation, New York, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
156628 ; 156656 ; 156659 ; 204 / ; 204 / ;
Abstract

A method of manufacturing a semiconductor device having a pattern of conductors, according to which method an auxiliary layer is formed which consists of two different sub-layers in which the negative of the desired pattern is provided and which is covered with a metal layer, in which the auxiliary layer and the said metal layer are then removed selectively. The method is characterized in that the auxiliary layer comprises a lowermost layer of an anodically oxidizable metal and an uppermost layer of the oxide of the said metal and may be used in the manufacture of semiconductor devices, especially transistors for very high frequencies and integrated circuits.


Find Patent Forward Citations

Rioult, Jean. (1977). Method of manufacturing a semiconductor device having a pattern of (U.S. Patent No. 4035206). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4035206

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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