Method of manufacturing a complementary metal-insulation-semiconductor

Abstract

A circuit comprised of interconnected complementary MIS devices is formed in a common semiconducting substrate by forming a plurality of complementary substrate regions in the common substrate, one region for each device whose source and drain regions are to have the same conductivity type as the common substrate. The other devices whose source and drain regions are to have the opposite conductivity type from that of the common substrate are formed directly therein. Interconnections between the devices are provided by a two-layer grid, the bottom layer of which is comprised of polycrystalline silicon conductors which also serve as the gates for the MIS devices. The top layer of the grid is comprised of a second set of conductors which is insulated from the bottom layer but which makes connection thereto and to the source and drain regions as well as to the complementary substrate at selected points. The regions of the substrate between adjacent MIS devices are covered by an oxide layer which extends both below and above the substrate surface and both ion implantation and the use of a doped oxide is disclosed for forming the complementary substrate regions.