The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 1977

Filed:

Nov. 10, 1975
Applicant:
Inventor:

Katsuaki Tsurushima, Kawasaki, JA;

Assignee:

Sony Corporation, Tokyo, JA;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03F / ;
U.S. Cl.
CPC ...
330 35 ; 330 13 ; 330 17 ; 330 22 ;
Abstract

A bias circuit particularly adapted for use with a field effect transistor whereby the drain bias current of the field effect transistor is maintained constant in the event of fluctuations in the operating voltage applied to the field effect transistor by a power supply. The bias circuit changes the gate bias voltage applied to the FET as a function of the fluctuations in the operating voltage to thereby restore the drain bias current to a constant value. A variable impedance is included in the bias circuit, the variable impedance being voltage dependent such that its impedance varies as the voltage applied thereto varies in accordance with a hyperbolic relation. The voltage applied to the variable impedance is derived from, and thus includes the fluctuations in, the operating voltage. The hyperbolic relation between the impedance and the voltage applied to the variable impedance effectively matches the relation between the pinch-off voltage V.sub.P and the amplification constant .mu. of the FET.


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