Data communications system with improved digital phase-locked loop

Abstract

A digital timing recovery circuit is disclosed for synchronously transmitting digitally encoded data in a multiterminal configuration between a data processor and a plurality of data terminals associated therewith. Phase shifted synchronous data from the data processor is continuously compared with a newly generated synchronous clock generated at a repeater interposed along the communication line for minimization of the time differential between the retiming clock and the transmitted data. The data transitions enable a digitally implemented one-shot, which generates pulses, the leading edges of which pulses enable a difference counter, while the leading edges of the retiming clock pulses disable the counter. The difference counter output is sampled in a digital phase locked loop to derive the number of cycles of a stable oscillator which occur between the two aforementioned leading edges of the generated pulses. A difference of less than a predetermined count such as two, results in no correction of the retiming clock, a difference count greater than such predetermined amount, such as a count of three through seven, advances the clock by adding a pulse to the retiming clock, and a difference of more than a predetermined number of counts, such as eight, retards the clock by subtracting a pulse from the retiming clock. Thus, continuous digital adjustment of the synchronous clock is provided to maintain the counter difference below a predetermined count, such as two, which serves to resynchronize bit-shifted data with the retiming clock for retransmission into the communications channel.