System for checking two data processors operating in parallel

Abstract

Two substantially identical data processors, operating in parallel, include each a general-purpose computer and an associated data store connected to each other by way of a respective logic network, the two networks being substantially identical and intercommunicating for recurrent comparisons of their settings. Each network includes a buffer memory for the temporary inscription of addresses in the corresponding data store together with data words to be read out of and into that store at the inscribed addresses, as well as a pair of counters respectively keeping track of the successive operating cycles initiated by computer instructions and of the checks performed on the results of these operations. Detection of a disparity by a comparator in either network results in a regression of the cycle counter to a preceding cycle which checked out correctly, with reintroduction of an earlier word from the buffer memory into the data store if the cancelled operation involved a writing step.