Digital double differential phase-locked loop

Abstract

A first generator provides a reference pulse train having a predetermined reference frequency. A second generator including a voltage controlled oscillator provides a bit clock having a repetition frequency locked to the repetition frequency of the bits of digital data. A first divider coupled to the first generator divides the reference frequency by a selected one of a first division factor and a second division factor different than the first division factor. A fourth divider coupled to the second generator divides the repetition frequency of the bit clock by a selected one of a third division factor and a fourth division factor different than the first, second and third division factors. A phase comparator coupled to the first and second dividers compare the phase of the output signals of the first and second dividers and produces a control signal proportional to the phase difference between the output signals of the first and second dividers. The control signal is coupled through a loop filter to the voltage controlled oscillator to lock the phase of the bit clock to the bits of the digital data. Logic circuitry coupled to the digital data source, the second generator and the first and second dividers produce a phase slip rate signal to select the appropriate one of the first and second division factors for the first divider and to select the appropriate one of the third and fourth division factors for the second divider.