Digital synchronizing signal recovery circuits for a data receiver

Abstract

A data signal stream includes, in a noisy signal channel, periodic word synchronization characters, and each such stream is preceded by a burst of predetermined bit rate information. An approximate bit rate timing signal is derived from the data stream and utilized for producing an initialization pulse when the predetermined bit rate information is detected. In addition, the approximate bit rate timing signal drives a digital phase-locked loop which is preset by the initialization pulse to a digital circuit state defining operation at the nominal frequency of the approximate bit rate timing signal. A stable bit clock signal provided by the phase-locked loop controls the operation of further circuits which are responsive to the baseband data stream for providing an indicator pulse each time that a synchronizing character appears in the data stream. The bit rate clock and the character indicator pulses are employed to operate a timing chain that yields word synchronization pulses in synchronism with the indicator pulses and having an extraordinarily low false-pulse rate as well as evidencing a flywheel effect to maintain word synchronization in the event that a small number of character indicating pulses are missed. If more such pulses are missed, the timing chain is resynchronized.