The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 1977

Filed:

Jan. 27, 1976
Applicant:
Inventors:

Piero Belforte, Turin, IT;

Giancarlo Guaschino, Turin, IT;

Giovanni Perucca, Turin, IT;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04J / ;
U.S. Cl.
CPC ...
179 / ;
Abstract

A processor in a telephone exchange, monitoring the activity of r subscriber lines having each an incoming and an outgoing channel allocated to them, emits during respective halves of any 8-bit time slot in a 32-time-slot frame a pair of m-bit addresses x, y for each subscriber initiating or engaged in a conversation, these addresses respectively identifying an outgoing channel of a first (e.g. calling) subscriber and an incoming channel of a second (e.g. called) subscriber to be placed once per frame in communication with each other by a PCM switching network. The addresses of incoming and outgoing channels issuing from the processor during each time slot are separated in a distributor, the addresses y being inscribed in stages of a storage network respectively assigned to the 32.sup.. 32.sup.. n channels identified by addresses x. The storage network consists of n random-access memories, one for each of n channel groups, divided into 32 sections of 32 stages each for as many 32-channel families. Each of 32 scanning intervals composed of n phases, occurring within a time slot, is reserved for the successive readout of homothetic stages in a respective set of n corresponding sections of all the memories, the set being divided into two subsets respectively scanned in the presence of relatively staggered enabling pulses also spanning n phases each whereby the readout of each subset starts after the beginning and terminates before the end of the corresponding enabling pulse.


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