The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 1977
Filed:
May. 27, 1975
Jerry Lee Highnote, Boulder, CO (US);
Richard Lewis O'Day, Boulder, CO (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A differential amplifier comprises a pair of Darlington configuration amplifier halves operating in the Class A mode. Each Darlington half is provided with a feedback, difference amplifier, which functions as an analog comparator, and an emitter current control resistor to precisely control the emitter current and thereby to control the idling or quiescent current passing through a load in the collector circuit. Each difference amplifier is connected to its respective half by coupling one of its two inputs to the control resistor in the Darlington emitter circuit and coupling the other input to a source of reference voltage. The respective emitter current control resistors are precisely matched. In operation, the output of each difference amplifier drives the base circuit of its respective Darlington half. The difference amplifier maintains the voltage at the terminal of the emitter current control resistor at a value substantially equal to the reference voltage, thereby biasing the Darlington half at a constant value representative of emitter current. Because the control resistors are precisely matched, the emitter currents are equal; and, because the gain of the Darlington halves is very high, the load or collector currents are substantially equal to the respective emitter currents and to one another. Thus, a load driven by both collector circuits is provided with a substantially zero d.c. offset current.