Static storage technique for four transistor igfet memory cell

Abstract

A four-IGFET memory cell is utilized as a static (or DC) memory cell rather than as a dynamic memory cell. When the memory cell is in the standby mode an intermediate voltage is applied to a selection conductor coupled to the gates of the gating IGFETS of the memory cell. The intermediate voltage applied to the 'X' selection conductor under standby conditions is slightly in excess of two IGFET threshold voltages, and is sufficient to maintain the stored logical state, yet causes very little power to be dissipated by the memory cell. A full logical '1' level is applied to the selection conductor during either a read operation or a write operation if the memory cell is selected, i.e. is addressed by the decoding circuitry in response to chip select and address inputs of a memory chip incorporating the memory cell. If the memory cell is unselected during a read or write operation, a logical '0' is applied to the selection conductor. A reference voltage circuit is provided on the semiconductor memory chip including an array of the four-IGFET memory cells in a preferred embodiment of the invention. The reference voltage circuit operates so that each row selection conductor, which is coupled to the gating IGFETS of a row of memory cells, is coupled to the reference voltage conductor when the semiconductor chip is unselected by a separate coupling IGFET coupled, respectively, between the reference voltage conductor and each of the selection conductors. Each selection conductor is also coupled to a selection circuit, which couples the selection conductor toward a V.sub.DD power supply voltage if the corresponding row has been selected by the decode circuitry and the chip is 'selected'. However, if the particular row is not selected, then the corresponding selection conductor is coupled by two IGFETS to a ground voltage supply conductor (if the chip is 'selected').