The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 10, 1977
Filed:
May. 10, 1976
Jeffrey R Fox, Waltham, MA (US);
William D Walsh, Franklin, MA (US);
GTE Laboratories Incorporated, Waltham, MA (US);
Abstract
A logic level converter converts an input signal having first and second voltage levels to an output signal having first and third voltage levels in which the voltage excursion of the output signal is greater than that of the input signal. The converter comprises first and second cross-coupled inverters in which the second inverter provides the output signal and is biased with respect to the first and third voltage levels and in which the first inverter is biased with respect to the third voltage level and the digital input signal. A voltage divider is associated with the first inverter to insure sufficient voltage swing for proper switching of the inverters. The inverters have dissimilar gains to insure that when the inverters are biased at equal voltages, the inverters always assume a predetermined state. The converter is implemented with PMOS field effect transistors and includes capacitors for increasing switching speed.