The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 1977
Filed:
Mar. 03, 1975
Rex Alan Naden, Richardson, TX (US);
Terry Wayne Noe, Richardson, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A packaging assembly for magnetic bubble chips comprising at least one module assembly board having a surface to which is secured in a substantially planar array a plurality of magnetic bubble chips for the storing and processing of information. First and second sets of terminals are located on opposed lateral edges of the module assembly board for the routing therethrough of information to and from the chips. First and second mounting boards are provided, each board having a set of receptacles for the soldering thereto of a corresponding set of the terminals. A first coil surrounds the module assembly board and is wound about an axis parallel to that of the plane of the chips for producing a magnetic field parallel thereto. A second coil surrounds the first coil and is wound about an axis perpendicular to that of the first coil and parallel to that of the plane of the chips for producing a magnetic field parallel thereto. A bias field source is positioned exterior to the second coil to produce a substantially constant magnetic field perpendicular to the plane of the chips. The first and second coils are excited to produce a rotating magnetic field parallel to the plane of the chips to control the movement of magnetic bubbles therein. Control components for the storage and processing of information in the chips are also provided. Convenient access to the chips may be gained by the sequential disassembly of the bias field source, the second coil, reheating the solder connection between the terminals and receptacles, and the first coil.