Semiconductor integrated circuit transistor detector array for channel

Abstract

In a channel electron multiplier device for detecting low level illumination optical image patterns, the output pattern of electrons is detected by an XY array of metal plates which are randomly accessed for readout by a corresponding row-column (XY) array of dual-gated insulated gate field effect transistors in an integrated circuit type of configuration. More specifically, each metal plate is located in the path of several (typically, ten or more) individual electron multiplier channels, in order to store the electrons emerging from these channels. The plates are all situated on the exposed surface of an insulating layer on a major surface of a semiconductor wafer. Each plate is connected through a different aperture in the insulating layer to a different localized source region of a different dual-gated insulated gate field effect transistor whose gate region is controlled by XY access control bus electrodes. These XY control bus electrodes are sandwiched in the insulating layer at levels in the insulator between the metal plates and the semiconductor wafer. Random XY access readout of the intensity of the electrons impinging on a given metal plate is obtained by energizing the crosspoint X and Y bus electrodes associated with that plate, and thereby the corresponding local intensity of the optical image portion, which produced the original photoelectrons in the channel multipliers associated with the accessed metal plate, can be determined.