Timing recovery circuit for digital data

Abstract

A timing recovery circuit receives a timing component signal and generates a signal having a frequency varying in response to a control signal. In response to a difference between the phase of the variable frequency signal and the phase of the timing component signal, the circuit produces a control component. In response to cycle slips between the variable frequency signal and the timing component signal, the circuit produces a series of pulses having a polarity related to the sense of the cycle slips and having a pulse rate directly related to the rate of the cycle slips except when amplitude of the timing component signals falls below a predetermined value whereupon no pulses are produced. The control component and the series of pulses are combined into the control signal that adjusts the frequency of the generated signal into synchronization with the timing component signal.