The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 1977

Filed:

Jul. 31, 1975
Applicant:
Inventors:

Mitsuhiko Ezoe, Yokohama, JA;

Hiroshige Ozawa, Yokohama, JA;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R / ;
U.S. Cl.
CPC ...
324 / ;
Abstract

Circuit testing apparatus includes a pulse oscillator providing clock pulses, a binary counter for counting the clock pulses to successively generate binary numbers, and a translator which translates the successive binary numbers into a series of test patterns. The test patterns include a series of input bit patterns used to energize the input leads of an electronic logic circuit under test and a series of output binary digits, each of which corresponds to the respective one of the input patterns. Each of the binary digits is compared with an output from the logic circuit under test. When the circuit tested is not functioning as prescribed for a particular set of input pattern, a noncoincidence signal will be produced to disable the binary counter in order to permit the test operator to register the test mode in which the trouble occurred. The binary counter may be enabled manually after registration to complete the prescribed number of tests. The presence of a noncoincidence signal is represented by binary digits and stored in a shift register. The stored bits are translated into information indicating the location of a circuit trouble, if any.


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