The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 1977

Filed:

Jun. 09, 1975
Applicant:
Inventor:

Pierre Leopold Gueret, Thalwil, CH;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
307212 ; 307277 ; 307306 ; 357-5 ;
Abstract

Logic elements comprising resettable Josephson junctions cooperating with matched transmission lines have input circuit inductances connected to reversible Josephson devices which are so small that a flux of less than one flux quantum only can be trapped therein preventing the continued circulation of supercurrent in the inductance after removal of the input signals from the associated reversible Josephson junctions. The resettable junctions are designed such that upon removal of the input or control field from the resettable Josephson junctions connected to the transmission line, the a.c. voltage which is generated across said junction, is larger than the time-average d.c. voltage across said junction when switched to its state of normal conductance so that, after removal of the input or control field from said junction, the d.c. voltage is caused to lock back to zero, thus resetting the element. Circuit parameters for achieving resettability without interrupting gate current are given. Logic circuits including AND, OR and NOT circuits are described and the conditions for the operation of such circuits which include both resettable and reversible Josephson devices are also given.


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