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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 4011467 B1

PDFFull Text
Date of Patent:
Mar. 08, 1977

Filed:

Feb. 18, 1976

Gate input circuit for insulated gate field effect transistors

Applicant:
Inventors:

Shunji Shimada, Kodaira, JA;

Kenichi Ohba, Fuchu, JA;

Shigeo Ishii, Tokyo, JA;

Assignee:

Hitachi, Ltd., , JA;

Attorney:

Craig & Antonelli

Primary Examiner:

John S Heyman

Assistant Examiner:

Larry N Anagnos

Int. Cl.
CPC ...
H03K / ; H03K / ; H02H / ;
U.S. Cl.
CPC ...
307251 ; 3072 / ; 307205 ; 307214 ; 307304 ; 361 54 ; 361 88 ;
Abstract

In a gate input circuit for insulated gate field effect transistors, an insulated gate field effect transistor of depletion type is used, whose drain electrode (or source electrode) is connected to one terminal of a power source and whose source electrode (or drain electrode) is short-circuited with the gate electrode and connected to an input terminal of the gate input circuit through a resistor.

Find Patent Forward Citations

Shimada, Shunji. (1977). Gate input circuit for insulated gate field effect transistors (U.S. Patent No. 4011467). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4011467

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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